1. Lecture 33 - Sequential Circuits & Latch
2. Notes 33 - Digital Logic Lecture 33 - Sequential Circuits & Latch Annotated Notes
3. Lecture 34 - Timing Diagram of SR Latch, Clock
4. Lecture 35 - Flipflops, SR Flipflop
5. Notes 34,35 - Digital Logic Lecture 34 FlipFlops SR Flipflop Annotated Notes
6. Lecture 36 - D Flipflop, Clock Triggering
7. Lecture 37 - T, JK Flipflops
8. Notes 36,37 - Digital Logic Lecture 36,37 D, JK, T FlipFlops Annotated Notes
9. Lecture 38 - Flipflop Conversion
10. Notes 38 - Digital Logic Lecture 38 Flipflop Conversion Annotated Notes
11. Lecture 39 - Preset & Clear Inputs
12. Notes 39 - Digital Logic Lecture 39 Flipflop Conversion, Preset, Clear Inputs Annotated Notes
13. Lecture 40 - Master Slave Flipflops
14. Notes 40 - Digital Logic Lecture 40 Master Slave FlipFlops, Race Condition Annotated Notes
15. Next Topic: Timing Issues in FlipFlops
16. Setup and Hold Time in Flip Flop | Timing Issues in Flip Flops
17. Duty Cycle, Clock Width, Clock Terminology
18. Example 1 : Setup and Hold Time in Flip Flop
19. Propagation Delay Vs Hold Time in Flip Flops
20. Timing Violations and Unpredictable Behavior in Flip Flops | Hold Time and Setup Time Violation
21. Minimum Clock Period | Maximum Clock Frequency Possible
22. Example 1 : Charles H. Roth Exercise 11.4 | Minimum Clock Period
23. Example 2 : Charles H. Roth 13.28 | Minimum Clock Period
24. Example 3 : NPTEL Question | Minimum Clock Period
25. GATE ECE 2020 | Maximum Frequency Possible
26. Notes - Timing Issues in Flipflops, Hold Time, Setup Time Annotated Notes
27. Next Topic: Registers
28. Introduction to Registers and Counters
29. Registers : Type of Registers
30. Shift Registers
31. Universal Shift Register, Bidirectional Shift Register
32. Linear Feedback Shift Register(LFSR) : Right Shift Register with ExOR GATE
33. GATE CSE 1987 Shift Register Question : 13-a
34. ISRO ECE 2010, 2007 Shift Register Question
35. GATE ECE 1992 Shift Register Question
36. GATE CSE 1991 Parallel In, Serial Out Shift Register Question
37. Applications of Shift Registers
38. GATE ECE 1996 Shift Register
39. Notes - Registers Annotated Lecture Notes
40. Next Topic: Finite State Machines (Mealy, Moore Models)
41. State of a Sequential Circuit, State Diagram, State Table, State Equation
42. Introduction to Finite State Machine FSM, Mealy Machine, Moore Machine
43. Finite State Machine(FSM) Design Example 1
44. Mealy Machine, Moore Machine
45. Mealy Moore Machine Design Example 1 : Increment a binary number by 1
46. Mealy Moore Machine Design Example 2 : Decrement a binary number by 1
47. Mealy Moore Machine Design Example 3 : 2s Complement of a binary number
48. Mealy Moore Machine Design Example 4 : Detect Sequence 01
49. GATE CSE 1994 Finite State Machine for Addition of two integers
50. GATE CSE 2002 Finite State Machine | Question: 2.5
51. GATE CSE 1995 Finite State Machine
52. GATE CSE 2005 Finite State Machine
53. GATE CSE 2009 Finite State Machine
54. GATE CSE 2006 Finite State Machine
55. Peter Linz Mealy, Moore Machine Question
56. GATE CSE 2021 Set 2 | Question: 28 | Mealy Machine
57. Notes - FSM Finite State Machine Mealy and Moore Machine Annotated Notes
58. Next Topic - Counters
59. Counters : Introduction
60. Asynchronous Counters Part 1 : Divide by 2 Counter, Frequency Division, Mod-2 counter | Part 1
61. Asynchronous Counters Part 2 : Divide by 4 Asynchronous Counters, Transient States, Mod-4 counters | Part 2
62. Notes - Counters, Asynchronous Counters Part 1,2 Annotated Notes
63. Asynchronous Counters Part 3 - Binary Ripple Counters, Transient States, Maximum Frequency
64. Asynchronous Counters Part 4 - Binary Up Ripple Counter, Mod-M Ripple Counters
65. Notes - Asynchronous Counters Part 3,4 - Binary Ripple Counter, Mod-M Counter Annotated Notes
66. Synchronous Counters Part 1 - Analysis
67. Synchronous Counters Part 2 - Design
68. Notes - Synchronous Counters Part 1,2 Design & Analysis Annotated Notes
69. Synchronous Counters: Ring Counter, Johnson Counter
70. Notes - Synchronous Counters Ring Counter, Johnson Counter Annotated Notes